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powerpc 750cx risc microprocessor datasheet version 1.2 june 20, 2001 ibm microelectronics division
notices before using this information and the product it supports, be sure to read the general information on the back cover of this document. trademarks the following are trademarks of international business machines corporation in the united states, or other countries, or both: ibm ibm logo powerpc aix powerpc 750 riscwatch other company, product, and service names may be trademarks or service marks of others. this is a preliminary edition of powerpc 750cx risc microprocessor datasheet. make sure you are using the correct edition for the level of the product . this document contains information on a new product under development by ibm. ibm reserves the right to change or discontinue this product without notice. ? international business machines corporation 2001. portions hereof ?international business machines corporation, 1991-2001. all rights reserved.
powerpc 750cx risc microprocessor datasheet june 20, 2001 version 1.2 page 3 table of contents 1.0. preface .................................................................................................................... .....................7 1.1. special design level considerations/features .....................................................................7 2.0. overview ................................................................................................................... ..................8 2.1. powerpc 750cx risc microprocessor block diagram .....................................................8 3.0. features ................................................................................................................... ....................9 4.0. general parameters ......................................................................................................... ..........11 5.0. electrical and thermal characteristics ..................................................................................... 11 5.1. dc electrical characteristics............................................................................................. ..11 5.2. ac electrical characteristics............................................................................................. ..14 5.2.1. clock ac specifications .........................................................................................14 5.3. 60x bus input ac specifications .......................................................................................16 5.4. 60x bus output ac specifications.....................................................................................17 5.4.1. ieee 1149.1 ac timing specifications .................................................................19 6.0. powerpc 750cx microprocessor dimension and physical signal assignments ....................22 7.0. system design information .................................................................................................. .....29 7.1. pll configuration......................................................................................................... ......29 7.2. pll power supply filtering................................................................................................ 31 7.3. decoupling recommendations............................................................................................31 7.4. connection recommendations ............................................................................................31 7.5. output buffer dc impedance..............................................................................................32 7.5.1. input-output usage .................................................................................................33 7.6. thermal management information......................................................................................36 7.7. heat sink considerations .................................................................................................. ..36 7.8. internal package conduction resistance.............................................................................36 7.9. operational and design considerations ..............................................................................38 7.9.1. level protection ......................................................................................................38 7.9.2. 64 or 32-bit data bus mode ...................................................................................38 7.9.3. 1.8v and 2.5v i/o signal support ..........................................................................38 7.9.4. dbw o/l2_tstclk ..............................................................................................39 7.9.5. powerpc 750cx revision level migration ...........................................................39 8.0. ordering information ....................................................................................................... .........39 9.0. processor version register (pvr) ........................................................................................... .40 10.0.document history .......................................................................................................... ...........41
powerpc 750cx risc microprocessor datasheet page 4 version 1.2 june 20, 2001 list of figures figure 1. powerpc 750cx risc microprocessor block diagram .............................................. 8 figure 2. sysclk input timing diagram ................................................................................... 15 figure 3. input timing diagram .................................................................................................. .. 16 figure 4. mode select input timing diagram ............................................................................... 17 figure 5. output valid timing definition ..................................................................................... 18 figure 6. output timing diagram for powerpc 750cx risc microprocessor .......................... 19 figure 7. jtag clock input timing diagram .............................................................................. 20 figure 8. trst timing diagram .................................................................................................. 21 figure 9. boundary-scan timing diagram ................................................................................... 21 figure 10. test access port timing diagram ................................................................................. 22 figure 11. pinout of the 256 pbga package as viewed from solder ball side ............................. 23 figure 12. side profile view of pbga ........................................................................................... 2 4 figure 13. side profile view showing exposed cavity .................................................................. 24 figure 14. powerpc 750cx microprocessor ball placement ......................................................... 25 figure 15. pll power supply filter circuit ................................................................................... 31 figure 16. driver impedance measurement .................................................................................... 32 figure 17. ibm riscwatch tm jtag to hreset, trst, and sreset signal connector ........ 36 figure 18. pbga package with thermal model ............................................................................. 37 figure 19. ibm part number key .................................................................................................. .40
powerpc 750cx risc microprocessor datasheet june 20, 2001 version 1.2 page 5 list of tables table 1: absolute maximum ratings ......................................................................................... 11 table 2: recommended operating conditions 1 ............................................................................................. 12 table 3: package thermal characteristics .................................................................................. 12 table 4: dc electrical specifications ......................................................................................... 13 table 5: power consumption ...................................................................................................... 14 table 6: clock ac timing specifications 1,6 ................................................................................................... 15 table 7: 60x bus input timing specifications 1,6,8 ....................................................................................... 16 table 8: 60x bus output ac timing specifications 1,4,6,7 ........................................................................ 17 table 9: jtag ac timing specifications (independent of sysclk) ...................................... 20 table 10: signal listing for the 256 pbga package ................................................................... 26 table 11: signals removed from previous powerpc 750 designs .............................................. 27 table 12: signal locations ...................................................................................................... ...... 28 table 13: voltage and ground assignments ................................................................................ 29 table 14: powerpc 750cx microprocessor pll configuration ................................................. 30 table 15: driver impedance characteristics ................................................................................. 32 table 16: input-output usage .................................................................................................... ... 34 table 17: summary of design migration ..................................................................................... 39 table 18: process version register (pvr) ................................................................................... 40 table 19: document history ...................................................................................................... ... 41
powerpc 750cx risc microprocessor datasheet page 6 version 1.2 june 20, 2001
powerpc 750cx risc microprocessor datasheet page 7 version 1.2 jun 20, 2001 1.0 preface the powerpc 750cx risc microprocessor is an implementation of the powerpc tm family of reduced instruction set computer (risc) microprocessors. this document contains pertinent physical characteristics of the powerpc 750cx risc microprocessor single chip modules (scm) and covers the following topics. ? overview on page 8 ? features on page 9 ? general parameters on page 11 ? electrical and thermal characteristics on page 11 - dc electrical characteristics on page 11 - ac electrical characteristics on page 14 ? powerpc 750cx microprocessor dimension and physical signal assignments on page 22 ? system design information on page 29 ? ordering information on page 39 ? processor version register (pvr) on page 40 1.1 special design level considerations/features the powerpc 750cx supports several unique features including those listed below. section 7.9 operational and design considerations, on page 38 provides a more detailed explanation of these. ? provides a 64 or 32-bit data bus mode (per setup of qa ck pin). ? supports 1.8v and 2.5v i/o signals. ? uses a reduced pin list from earlier powerpc 750 designs (see table 11, signals removed from previous powerpc 750 designs on page 27). ? data bus write only ( dbw o) shares a common pin with l2_testclk. ? ckstp_out shares a common pin with clk_out.
powerpc 750cx risc microprocessor datasheet page 8 version 1.2 jun 20, 2001 2.0 overview the powerpc 750cx risc microprocessor is targeted for high performance, low power systems and a 60x bus. the powerpc 750cx risc microprocessor also includes an internal (256kbyte) l2 cache with on-board error correction circuitry (ecc). 2.1 powerpc 750cx risc microprocessor block diagram figure 1 shows a block diagram of the powerpc 750cx risc microprocessor. figure 1. powerpc 750cx risc microprocessor block diagram gprs lsu fpu instruction fetch system completion rename buffers unit 32k icache bht / biu 60x l2 cache fxu2 dispatch branch unit btic control unit fprs rename buffers 256k 32k dcache l2 tags fxu1
powerpc 750cx risc microprocessor datasheet jun 20, 2001 version 1.2 page 9 3.0 features this section summarizes the features of the powerpc 750cxs implementation of the powerpc architecture. major fea- tures of the powerpc 750cx are as follows. ? branch processing unit - four instructions fetched per clock - one branch processed per cycle (plus resolving 2 speculations) - up to 1 speculative stream in execution, 1 additional speculative stream in fetch - 512-entry branch history table (bht) for dynamic prediction - 64-entry, 4-way set associative branch target instruction cache (btic) for eliminating branch delay slots ? dispatch unit - full hardware detection of dependencies (resolved in the execution units) - dispatch two instructions to six independent units (system, branch, load/store, ?xed-point unit 1, ?xed-point unit 2, or ?oating-point) - 4-stage pipeline: fetch, dispatch, execute, and complete - serialization control (predispatch, postdispatch, execution, serialization) ? decode - register ?le access - forwarding control - partial instruction decode ? load/store unit - one cycle load or store cache access (byte, half-word, word, double-word) - effective address generation - hits under misses (one outstanding miss) - single-cycle misaligned access within double word boundary - alignment, zero padding, sign extend for integer register ?le - floating-point internal format conversion (alignment, normalization) - sequencing for load/store multiples and string operations - store gathering - cache and tlb instructions - big and little-endian byte addressing supported - misaligned little-endian support in hardware ? fixed-point units - fixed-point unit 1 (fxu1); multiply, divide, shift, rotate, arithmetic, logical - fixed-point unit 2 (fxu2); shift, rotate, arithmetic, logical - single-cycle arithmetic, shift, rotate, logical - multiply and divide support (multi-cycle) - early out multiply - thirty-two, 32-bit general purpose registers - secondary fxu executes integer add/compare instructions ? floating-point unit - support for ieee-754 standard single and double-precision ?oating-point arithmetic - optimized for single-precision multiply/add - thirty-two, 64-bit ?oating point registers - enhanced reciprocal estimates - 3-cycle latency, 1-cycle throughput, single-precision multiply-add - 3-cycle latency, 1-cycle throughput, double-precision add - 4-cycle latency, 2-cycle throughput, double-precision multiply-add
powerpc 750cx risc microprocessor datasheet page 10 version 1.2 jun 20, 2001 ? floating-point unit (continued) - hardware support for divide - hardware support for denormalized numbers - time deterministic non-ieee mode ? system unit - executes cr logical instructions and miscellaneous system instructions - special register transfer instructions ? l1 cache structure - 32k, 32-byte line, 8-way set associative instruction cache - 32k, 32-byte line, 8-way set associative data cache - single-cycle cache access - pseudo-lru replacement - copy-back or write-through data cache (on a page per page basis) - 3-state (mei) memory coherency - hardware support for data coherency - non-blocking instruction and data cache (one outstanding miss under hits) - no snooping of instruction cache ? memory management unit - 128 entry, 2-way set associative instruction tlb - 128 entry, 2-way set associative data tlb - hardware reload for tlb's - 4 instruction bats and 4 data bats - virtual memory support for up to 4 exabytes (2 52 ) virtual memory - real memory support for up to 4 gigabytes (2 32 ) of physical memory - support for big/little-endian addressing ? level 2 (l2) cache - internal l2 cache controller and 4k-entry tags; 256k data srams - copy-back or write-through data cache on a page basis, or for all l2 - 64-byte sectored line size - l2 frequency at core speed - on-board ecc ? bus interface - compatible with 60x processor interface (some pin functions removed, see table 11, signals removed from previous powerpc 750 designs on page 27) - 32-bit address bus - 64-bit data bus (or 32-bit mode) - core-to-bus frequency multipliers of 2x, 2.5x, 3x, 3.5x, 4x, 4.5x, 5x, 5.5x, 6x, 6.5x, 7x, 7.5x, 8x, and 10x supported ? power - under 4 watts typical @ 400mhz ? testability - lssd scan design - powerful diagnostic and test interface through common on-chip processor (cop) and ieee 1149.1 (jtag) interface
powerpc 750cx risc microprocessor datasheet jun 20, 2001 version 1.2 page 11 4.0 general parameters the following list provides a summary of the general parameters of the powerpc 750cx. technology 0.18 m m cmos copper technology, six-layer metallization die size 42.7 sq. mm transistor count 20 million - including l2 cache logic design fully-static package surface mount 256-lead plastic ball grid array (pbga) 27x27mm core power supply 1.8v +/- 5% i/o power supply 1.8v +/- 5% 2.5v +/- 5% 5.0 electrical and thermal characteristics this section provides both ac and dc electrical speci?cations and thermal characteristics for the powerpc 750cx. 5.1 dc electrical characteristics the tables in this section describe the powerpc 750cx risc microprocessors dc electrical characteristics. table 1 provides the absolute maximum ratings. table 1: absolute maximum ratings characteristic symbol value (bvsel = 0) value (bvsel = 1) unit core supply voltage v dd -0.3 to 2.0 -.03 to 2.00 v pll supply voltage av dd -0.3 to 2.0 -0.3 to 2.00 v 60x bus supply voltage ov dd -0.3 to 2.0 -0.3 to 2.75 v input voltage v in -0.3 to 2.0 -0.3 to 2.75 v storage temperature range t stg -55 to 150 -55 to 150 c note: 1. functional and tested operating conditions are given in table 2, recommended operating conditions 1 on page 12. absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. stresses beyond those listed above may affect device reliability or cause permanent damage to the device. 2. caution: v in must not exceed ov dd by more than 0.6v at any time, including during power-on reset. 3. caution: ov dd must not exceed v dd /av dd by more than 2.0v, except for up to 20ms during power on/off reset. 4. caution: v dd /av dd must not exceed ov dd by more than 1.2v, except for up to 20ms during power up/down. 5. caution: av dd must not exceed v dd by more than 1.2v, except for up to 20ms during power up/down reset.
powerpc 750cx risc microprocessor datasheet page 12 version 1.2 jun 20, 2001 table 2 provides the recommended operating conditions for the powerpc 750cx. table 3 provides the package thermal characteristics for the powerpc 750cx. table 2: recommended operating conditions 1 characteristic symbol value unit core supply voltage v dd 1.70 to 1.90 v pll supply voltage av dd 1.70 to 1.90 v 60x bus supply voltage (1.8v mode) ov dd 1.70 to 1.90 v 60x bus supply voltage (2.5v mode) ov dd 2.375 to 2.625 v input voltage v in gnd to ov dd v die-junction temperature t j 0 to 105 c note: these are recommended and tested operating conditions. proper device operation outside of these conditions is not guaran teed. 1. see figure 19, for applicaiton conditions table 3: package thermal characteristics characteristic symbol value unit pbga package thermal resistance, junction to ambient, thermal resistance, convection only * q ja 15.9 c/w pbga package thermal resistance, junction-to-ambient thermal resistance, 100 linear ft. per minute* q ja 13.9 c/w pbga package thermal resistance, junction-to-board thermal resistance q jb 7.4 c/w pbga package thermal resistance, junction-to-case thermal resistance q jc 0.7 c/w note: * assumes that the package is soldered to a 2s2p board.
powerpc 750cx risc microprocessor datasheet jun 20, 2001 version 1.2 page 13 table 4 provides dc electrical characteristics for the powerpc 750cx. table 4: dc electrical speci?cations see table 2 on page 12 for recommended operating conditions. characteristic symbol voltage unit notes min max input high voltage (all inputs except sysclk) v ih (1.8v) 1.24 1.90 v 2,4 v ih(2.5v) 1.70 2.625 v 2 input low voltage (all inputs except sysclk) v il(1.8v) gnd 0.60 v 4 v il(2.5v) gnd 0.70 v sysclk input high voltage cv ih(1.8v) 1.20 1.90 v cv ih(2.5v) 1.90 2.625 v sysclk input low voltage cv il(1.8v) gnd 0.4 v input leakage current, v in = ov dd = 2.5v i in C20 m a3 input leakage current, v in = ov dd = 1.8v i in C20 m a3 hi-z (off state) leakage current, v in = ov dd = 2.5v i tsi C20 m a3 hi-z (off state) leakage current, v in = ov dd = 1.8v i tsi C20 m a3 output high voltage, i oh = C4ma v oh(1.8v) 1.30 C v v oh(2.5v) 2.00 C v output low voltage, i ol = 4ma v ol(1.8v, 2.5v) C 0.4 v capacitance, v in =0 v, f = 1mhz c in C 5.0 pf 1 note: 1. capacitance values are guaranteed by design and characterization, and are not tested. 2. maximum input high voltage for short duration (not continuous operation). 3. additional input current may be attributed to the level protection keeper lock circuity. for details, see section 7.9 on page 38. 4. v ih and v il minimum levels are set as a percentage of v dd . v ih is 65% and v il is 35% respectively.
powerpc 750cx risc microprocessor datasheet page 14 version 1.2 jun 20, 2001 table 5 provides the power consumption for the powerpc 750cx. 5.2 ac electrical characteristics this section provides the ac electrical characteristics for the powerpc 750cx. after fabrication, parts are sorted by maximum processor core frequency as shown in the section 5.2.1 on page 14, and tested for conformance to the ac speci?cations for that frequency. the processor core frequency is determined by the bus (sysclk) frequency and the settings of the pll_cfg(0-3) signals. 5.2.1 clock ac speci?cations table 6 provides the clock ac timing speci?cations as de?ned in figure 2. table 5: power consumption see table 2 on page 12 for recommended operating conditions. representative processor frequency unit notes 366mhz 400mhz 466mhz 500mhz full-on mode typical ( v dd = 1.8v) (ov dd =1.8)(65c) 3.3 3.5 4.0 4.3 w 1,3,4,5 maximum ( v dd = 1.9v) (ov dd =1.9)(105c) 6.7 7.1 7.7 8.3 w 1,2,4,5 typical ( v dd = 1.8v) (ov dd =2.5)(65c) 3.3 3.5 4.0 4.3 w 1,3,4,5 maximum ( v dd = 1.9v) (ov dd =2.62)(105c) 6.7 7.1 7.7 8.3 w 1,2,4,5 doze mode maximum ( v dd = 1.9v) (ov dd =1.9)(105c) 3.7 4.0 4.5 4.6 w 1,2,4,5 nap mode maximum (v dd = 1.9v) (ov dd =1.9)(105c ) 1.5 1.5 1.6 1.7 w 1,2,4,5 sleep mode maximum ( v dd = 1.9v) (ov dd =1.9)(105c) 1.4 1.4 1.5 1.6 w 1,2,4,5 note: 1. these values apply for all valid 60x buses. the values do not include i/o supply power (ov dd ) or pll/dll supply power (av dd ). ov dd power is system dependent, but is typically <10% of v dd power. 2. maximum power is measured at v dd = 1.90v and assumes worst case process parameters. 3. typical power is an estimate of the average value measured at v dd =av dd = 1.8v, ov dd = 1.80/2.5v in a system executing typical applica- tions and benchmark sequences. 4. full-on mode uses a worst case instruction mix. 5. guaranteed by design and characterization, and is not tested.
powerpc 750cx risc microprocessor datasheet jun 20, 2001 version 1.2 page 15 figure 2. sysclk input timing diagram table 6: clock ac timing speci?cations 1,6 see table 2 on page 12, for recommended operating conditions. num characteristic value unit notes min max processor frequency 300 500 mhz 6 sysclk frequency 31 133 mhz 1 1 sysclk cycle time 7.5 32 ns 2,3 sysclk rise and fall time (slew rate) 1.0 2.0 volt/ns 2,3 4 sysclk duty cycle measured at 0.8v 25 75 % 3 sysclk jitter C 150 ps 4,3 internal pll relock time C 100 m s5 note: 1. caution: the sysclk frequency and the pll_cfg[0-3] settings must be chosen such that the resulting sysclk (bus) frequency, cp u (core) fre- quency, and pll (vco) frequency do not exceed their respective maximum or minimum operating frequencies. refer to the pll_cfg[0 -3] signal description in section pll configuration, on page 28 for valid pll_cfg[0-3] settings. 2. rise and fall times for the sysclk input are measured from 0.4 to 1.2v. 3. timing is guaranteed by design and characterization, and is not tested. 4. the total input jitter (short term and long term combined) must be under 150ps. 5. relock timing is guaranteed by design and characterization, and is not tested. pll-relock time is the maximum amount of time required for pll lock after a stable v dd and sysclk are reached during the power-on reset sequence. this specification also applies when the pll has been disabled and subsequently re-enabled during sleep mode. also note that hreset must be held asserted for a minimum of 255 bus clocks after the pll-relock time during the power-on reset sequence. 6. for applications with processor frequencies below 300mhz, application conditions need to be investigated. vm cv il cv ih 1 2 4 3 4 sysclk vm - midpoint voltage (0.8v)
powerpc 750cx risc microprocessor datasheet page 16 version 1.2 jun 20, 2001 5.3 60x bus input ac speci?cations table 7 provides the 60x bus input ac timing speci?cations for the powerpc 750cx as de?ned in figure 3 and figure 4. figure 3 provides the input timing diagram for the powerpc 750cx. table 7: 60x bus input timing speci?cations 1,6,8 see table 2 on page 12 for operating conditions. num characteristic 1.8v mode 2.5v mode unit notes min max. min. max. 10a address/data/transfer attribute inputs valid to sysclk (input setup) 1.4 1.4 ns 2 10b all other inputs valid to sysclk (input setup) 1.4 1.4 ns 3 10c mode select input setup to hreset ( qa ck) 88t sysclk 4,5,7 10d ts to sysclk (input setup) 1.6 1.6 10e dbw o to sysclk (input setup) 2.1 2.1 11a sysclk to inputs invalid (input hold) 1.2 1.2 ns 2 11b hreset to mode select input hold ( qa ck) 0 0 ns 4,7 note: 1. input specifications are measured from the midpoint voltage (0.9v) of the signal in question to the midpoint voltage of the r ising edge of the input sysclk. input and output timings are measured at the pin (see figure 3). 2. address/data transfer attribute inputs are composed of all bidirectional and input signals except those listed in note 3. 3. all other signal inputs are composed of the following: ta, qack, and artry. 4. the setup and hold time is with respect to the rising edge of hreset (see figure 4 on page 17). 5. t sysclk , is the period of the external clock (sysclk) in nanoseconds (ns). the numbers given in the table must be multiplied by the period of sysclk to compute the actual time duration (in ns) of the parameter in question. 6. these values are guaranteed by design, and are not tested. 7. this specification is for configuration mode select only. also note that the hreset must be held asserted for a minimum of 255 bus clocks after the pll relock time during the power-on reset sequence. 8. these timings are valid for processor frequencies up to 466mhz. 500mhz timing behavior and characterization is being evaluate d at this time. figure 3. input timing diagram vm sysclk all inputs vm = midpoint voltage (0.8v for sysclk, 0.9v for all other i/o) 10b 10a 11a vm vm 10d 10e
powerpc 750cx risc microprocessor datasheet jun 20, 2001 version 1.2 page 17 figure 4 provides the mode select input timing diagram for the powerpc 750cx. 5.4 60x bus output ac speci?cations table 8 provides the 60x bus output ac timing speci?cations for the powerpc 750cx as de?ned in figure 6 on page 19. figure 4. mode select input timing diagram table 8: 60x bus output ac timing speci?cations 1,4,6,7 see table 2 on page 12 for operating conditions. num characteristic 1.8v mode 2.5v mode unit notes min. max. min. max. 12 sysclk to output driven (output enable time) 0.3 0.3 ns 13 sysclk to output valid C 2.31 C 2.61 ns 14 sysclk to output invalid (output hold) 0.400 0.400 ns 2 15 sysclk to output high impedance (all signals except artry) C 2.5 C 2.5 ns 16 sysclk to artry high impedance before precharge C 3.0 C 3.0 ns 17 sysclk to artry precharge enable 0.2 * t sysclk + 1.0 0.2 * t sysclk + 1.0 ns 2, 3, 5 18 maximum delay to artry precharge 1 1 t sysclk 3, 5 19 sysclk to artry high impedance after precharge 2 2 t sysclk 3, 5 note: 1. all output specifications are measured from the midpoint voltage (0.8v) of the rising edge of sysclk to the midpoint voltage of the signal in question defined in figure 5. both input and output timings are measured at the pin. timings are determined by design. 2. this minimum parameter assumes cl = 0pf. 3. t sysclk is the period of the external bus clock (sysclk) in nanoseconds (ns). the numbers given in the table must be multiplied by the period of sysclk to compute the actual time duration of the parameter in question. 4. output signal transitions are defined in figure 5. 5. nominal precharge width for artry is 1.0 t sysclk . 6. guaranteed by design and characterization, and not tested. 7. these timings are valid for processors up to 466mhz. 500mhz processor timing behavior and characterization are being evaluate d at this time. v ih v ih = 1.24v mode pins 10c 11b hreset 10c 11b
powerpc 750cx risc microprocessor datasheet page 18 version 1.2 jun 20, 2001 figure 5. output valid timing de?nition 65 ohm line output driver sysclk positive output transition negative output transition 1/4 ov dd 3/4 ov dd output transition de?ned between sysclk @ 0.8v and the respective transition level. (note: the timing de?nition uses an in?nitely long transmission line model.) vmeasure
powerpc 750cx risc microprocessor datasheet jun 20, 2001 version 1.2 page 19 5.4.1 ieee 1149.1 ac timing speci?cations table 9 provides the ieee 1149.1 (jtag) ac timing speci?cations as de?ned in figure 7, figure 8, figure 9, and figure 10. the ?ve jtag signals are; tdi, tdo, tms, tck, and trst. figure 6. output timing diagram for powerpc 750cx risc microprocessor sysclk all outputs (except ts, artry) ts artry 12 13 13 14 15 15 vm vm 14 vm 13 18 16 19 17 vmeasure vmeasure vmeasure low level hi-z high level vmeasure is defined with reference to figure 5 as 1/4 of the transition of ov dd .
powerpc 750cx risc microprocessor datasheet page 20 version 1.2 jun 20, 2001 figure 7 provides the jtag clock input timing diagram. table 9: jtag ac timing speci?cations (independent of sysclk) see table 2 on page 12 for operating conditions.. num characteristic min max unit notes tck frequency of operation 0 25 mhz 1 tck cycle time 40 ns 2 tck clock pulse width measured at 1.1v 15 ns 3 tck rise and fall times 0 2 ns 4 4 specification obsolete, intentionally omitted 5 trst assert time 25 ns 1 6 boundary-scan input data setup time 0 ns 2 7 boundary-scan input data hold time 13 ns 2 8 tck to output data valid C 8 ns 3, 5 9 tck to output high impedance 3 19 ns 3, 4 10 tms, tdi data setup time 0 ns 11 tms, tdi data hold time 15 ns 12 tck to tdo data valid 2.5 12 ns 5 13 tck to tdo high impedance 3 9 ns 4 14 tck to output data invalid (output hold) 0 C ns note: 1. trst is an asynchronous level sensitive signal. guaranteed by design. 2. non-jtag signal input timing with respect to tck. 3. non-jtag signal output timing with respect to tck. 4. guaranteed by characterization and not tested. 5. minimum specification guaranteed by characterization and not tested. figure 7. jtag clock input timing diagram 1 2 2 3 3 vm = midpoint voltage (0.9v) vm tck vm vm
powerpc 750cx risc microprocessor datasheet jun 20, 2001 version 1.2 page 21 figure 8 provides the trst timing diagram. figure 9 provides the boundary-scan timing diagram. figure 8. trst timing diagram figure 9. boundary-scan timing diagram 5 trst 9 6 7 8 9 tck data inputs data outputs data outputs input data valid output data valid
powerpc 750cx risc microprocessor datasheet page 22 version 1.2 jun 20, 2001 figure 10 provides the test access port timing diagram. 6.0 powerpc 750cx microprocessor dimension and physical signal assignments ibm offers a plastic ball grid array, pbga, which supports 256 balls as the powerpc 750cx package. the following sections contain several views of the package, pin information, and a pin listing. figure 11 shows the pinout of the 256 pbga package as viewed from the solder ball surface. figure 12 shows the side pro?le of the 256 pbga package including the height from the top of the copper heat spreader to the bottom of the sol- der balls. figure 13 provides a more detailed side pro?le including the encapsulant (glob) referenced. figure 10. test access port timing diagram 12 10 11 tck tdi, tms tdo tdo input data (valid) output data (valid) tdo 13 14 output data (invalid)
powerpc 750cx risc microprocessor datasheet jun 20, 2001 version 1.2 page 23 . figure 11. pinout of the 256 pbga package as viewed from solder ball side abcdefghj klmnprt 01 02 04 05 06 07 08 09 10 11 12 13 15 16 17 18 19 uvw 20 y 03 14 d d1 q e e1 dimension nominal length (mm) c 15.1 max d 27.00 d1 24.13 e 27.00 e1 24.13 q 1.27 c
powerpc 750cx risc microprocessor datasheet page 24 version 1.2 jun 20, 2001 figure 12. side pro?le view of pbga figure 13. side pro?le view showing exposed cavity item description length (mm) height (mm) a cu heat spreader 27 .356 b laminate including plating 27 .585 c solder ball n/a .60 d chip cavity 15.1 max n/a e minimum glop to solder ball height n/a .244 f cu heat spreader, laminate, bond pads, and plating n/a .955 note: dimension a consists of the entire package with solder balls before re?ow. dimension nominal (mm) a 1.539 a a b c d e nickel plated surface bond pads and solder mask f
powerpc 750cx risc microprocessor datasheet jun 20, 2001 version 1.2 page 25 figure 14. powerpc 750cx microprocessor ball placement (above view is looking down from above the powerpc 750cx placed and soldered on the system board.) ** dbw o multiplexed with l2_tstclk function, see section 7.9.4 on page 39 for details. 1 2 3 4 5 6 7 8 9 1011121314151617181920 a g g dh3 g dh9 dh11 dh13 dh15 dh16 dh19 dh20 dh23 dh24 dh26 dh28 dh30 g a4 g g b g g vdd dh4 dh6 dh8 dh12 g dh18 g g dh21 g dh27 dh31 a1 a3 vdd g g c dh2 vdd g vdd ovdd dh7 dh10 dh14 dh17 g g dh22 dh25 dh29 a0 ovdd vdd g vdd a5 d ovdd dh1 vdd g vdd dh5 ovdd vdd ovdd vdd vdd ovdd vdd ovdd a2 vdd g vdd a6 g e hreset dh0 dbw o* vdd vdd ovdd a8 a11 f pllcfg0 lssd_mode mcp l1_tstclk a7 a9 a10 a13 g pllcfg2 pllcfg1 sysclk ovdd ovdd a12 a14 a15 h bvsel pllcfg3 avdd vdd vdd tt_0 g tt_1 j g int ckstp_in ovdd ovdd tt_3 ts tt_2 k sreset qack g vdd vdd g g tt_4 l qreq g g vdd vdd g g tsiz0 m dbg tea artry ovdd ovdd tsiz2 tsiz1 ta n br g tdo vdd vdd aac kg tbst p bg ckstp_out tdi ovdd ovdd a19 a17 a16 r wt gb l tms trst a24 a22 a21 a18 t dl31 ci tck vdd vdd ovdd a23 a20 u ovdd dl30 vdd g vdd dl26 ovdd vdd ovdd vdd vdd ovdd vdd ovdd a29 vdd g vdd a25 g v dl29 vdd g vdd ovdd dl24 dl21 dl17 dl14 g g dl9 dl6 dl2 a31 ovdd vdd g vdd a26 w g g vdd dl27 dl25 dl23 dl19 g dl13 g g dl10 g dl4 dl0 a30 a28 vdd g g y g g dl28 g dl22 dl20 dl18 dl16 dl15 dl12 dl11 dl8 dl7 dl5 dl3 dl1 g a27 g g
powerpc 750cx risc microprocessor datasheet page 26 version 1.2 jun 20, 2001 table 10: signal listing for the 256 pbga package signal name pin count active i/o notes a0-a31 32 high i/o aack 1 low input artry 1 low i/o bg 1 low input br 1 low output ci 1 low output ckstp_in 1 low input ckstp_out 2 1 low output dbg 1 low input dh0-dh31 32 high i/o dl0-dl31 32 high i/o gbl 1 low i/o hreset 1 low input int 1 low input l1_tstclk 1 1 high input dbwo/l2_tstclk 1,2,3 1 high input lssd_mode 1 1 low input mcp 1 low input pll_cfg[0-3] 4 high input qa ck 2 1 low input optional: 64/ 32-bit data bus mode select. this function will be set when hreset transitions (low to high). qack: low = 64-bit mode, high =32-bit mode. qreq 1 low output sreset 1 low input sysclk 1 input ta 1 low input tbst 1 low i/o tck 1 high input tdi 1 high input tdo 1 high output tea 1 low input tms 1 high input trst 1 low input note: 1. these are test signals for factory use only and must be pulled up to ov dd for normal machine operation. 2. the ckstp_out signal in test mode allows viewing the powerpc 750cx risc microprocessor internal clocks. the qack signal allows selection of 32-bit mode.(see the powerpc 750cx risc microprocessor users manual for more information.) 3. l2-tstclk in normal mode is dbwo , for details, see section 7.9.4 on page 39.
powerpc 750cx risc microprocessor datasheet jun 20, 2001 version 1.2 page 27 ts 1 low i/o tsiz0-tsiz2 3 high output tt0-tt4 5 high i/o wt 1 low output bvsel 1 high input pin set low = 1.8v , pin set high = 2.5v (this is supported for dd2.x) av dd 1 supply for pll ov dd 24 supply for receiver/drivers v dd 40 supply for core ground 53 common ground table 11: signals removed from previous powerpc 750 designs signal name pin count active i/o notes abb 1 low i/o dbb 1 low i/o dbdis 1 low input rsrv 1 low output smi 1 low input tben 1 high input voltdet 1 high output ap0-3 4 high i/o dp0-7 8 high i/o drtry 1 low input tlbisync 1 low input table 10: signal listing for the 256 pbga package (cont.) signal name pin count active i/o notes note: 1. these are test signals for factory use only and must be pulled up to ov dd for normal machine operation. 2. the ckstp_out signal in test mode allows viewing the powerpc 750cx risc microprocessor internal clocks. the qack signal allows selection of 32-bit mode.(see the powerpc 750cx risc microprocessor users manual for more information.) 3. l2-tstclk in normal mode is dbwo , for details, see section 7.9.4 on page 39.
powerpc 750cx risc microprocessor datasheet page 28 version 1.2 jun 20, 2001 table 12: signal locations signal ball location signal ball location signal ball location signal ball location a0 c15 dh0 e2 dl0 w15 aa ck n18 a1 b16 dh1 d2 dl1 y16 ar tr ym3 a2 d15 dh2 c1 dl2 v14 bg p1 a3 b17 dh3 a3 dl3 y15 br n1 a4 a18 dh4 b4 dl4 w14 bvsel h1 a5 c20 dh5 d6 dl5 y14 ci t2 a6 d19 dh6 b5 dl6 v13 ckstp_in j3 a7 f17 dh7 c6 dl7 y13 ckstp_out p2 a8 e19 dh8 b6 dl8 y12 dbg m1 a9 f18 dh9 a5 dl9 v12 gbl r2 a10 f19 dh10 c7 dl10 w12 hreset e1 a11 e20 dh11 a6 dl11 y11 int j2 a12 g18 dh12 b7 dl12 y10 l1_tstclk f4 a13 f20 dh13 a7 dl13 w9 dbwo/l2_tstclk 1 e3 a14 g19 dh14 c8 dl14 v9 lssd_mode f2 a15 g20 dh15 a8 dl15 y9 mcp f3 a16 p20 dh16 a9 dl16 y8 pll_cfg0 f1 a17 p19 dh17 c9 dl17 v8 pll_cfg1 g2 a18 r20 dh18 b9 dl18 y7 pll_cfg2 g1 a19 p18 dh19 a10 dl19 w7 pll_cfg3 h2 a20 t20 dh20 a11 dl20 y6 qack (also used for 64/32-bit db select.) k2 a21 r19 dh21 b12 dl21 v7 qreq l1 a22 r18 dh22 c12 dl22 y5 sreset k1 a23 t19 dh23 a12 dl23 w6 sysclk g3 a24 r17 dh24 a13 dl24 v6 t a m20 a25 u19 dh25 c13 dl25 w5 tbst n20 a26 v20 dh26 a14 dl26 u6 tck t3 a27 y18 dh27 b14 dl27 w4 tdi p3 a28 w17 dh28 a15 dl28 y3 tdo n3 a29 u15 dh29 c14 dl29 v1 tea m2 a30 w16 dh30 a16 dl30 u2 tms r3 a31 v15 dh31 b15 dl31 t1 trst r4 ts j19 tsiz0 l20 tsiz1 m19 tsiz2 m18 tt0 h18 tt1 h20 tt2 j20 tt3 j18 tt4 k20 wt r1 1. see section 7.9.4 on page 39 for a detailed discussion.
powerpc 750cx risc microprocessor datasheet jun 20, 2001 version 1.2 page 29 7.0 system design information this section provides electrical and thermal design recommendations for successful application of the powerpc 750cx. 7.1 pll con?guration the powerpc 750cx pll is con?gured by the pll_cfg[0-3] signals. for a given sysclk (bus) frequency, the pll con?guration signals set the internal cpu and vco frequency of operation. the pll con?guration for the powerpc 750cx is shown in the following table for nominal frequencies. table 13: voltage and ground assignments av dd ov dd v dd v dd gnd gnd h3 m4 b3 l4 a1 l3 m17 b18 l17 a2 l18 p4 c2 n4 a4 l19 p17 c4 n17 a17 n2 t18 c17 t4 a19 n19 u1 c19 t17 a20 u4 u7 d3 u3 b1 u17 u9 d5 u5 b2 u20 u12 d8 u8 b8 v3 u14 d10 u10 b10 v10 v5 d11 u11 b11 v11 v16 d13 u13 b13 v18 c5 d16 u16 b19 w1 c16 d18 u18 b20 w2 d1 e4 v2 c3 w8 d7 e17 v4 c10 w10 d9 h4 v17 c11 w11 d12 h17 v19 c18 w13 d14 k4 w3 d4 w19 e18 k17 w18 d17 w20 g4 d20 y1 g17 h19 y2 j4 j1 y4 j17 k3 y17 k18 y19 k19 y20 l2
powerpc 750cx risc microprocessor datasheet page 30 version 1.2 jun 20, 2001 table 14: powerpc 750cx microprocessor pll con?guration pll_cfg (0:3) processor to bus frequency ratio (r) frequency range supported by vco having an example range of vco min = 500 to vco max = 1ghz 6 sysclk core bin dec min max min max 0000 0 2.5x 120 133 5 300 333 0001 1 7.5x 40 67 300 500 6 0010 2 7x 43 71 0011 3 pll bypass 3 n/a n/a n/a n/a 0100 4 2x note 1 note 1 note 1 note 1 0101 5 6.5x 46 77 300 500 6 0110 6 10x 31 2 50 310 500 6 0111 7 4.5x 66 111 300 500 6 1000 8 3x 100 133 5 1001 9 5.5x 55 109 1010 10 4x 75 150 1011 11 5x 40 120 1100 12 8x 37 75 1101 13 6x 50 100 1110 14 3.5x 85 172 1111 15 off 4 n/a n/a off off note: 1. the 2x processor to bus ratio is currently not supported. 2. sysclk min is limited by the lowest frequency that manufacturing will support, see section clock ac specifications on page 14 for valid sysclk and vco frequencies. 3. in pll-bypass mode, the sysclk input signal clocks the internal processor directly, the pll is disabled, and the bus mode is set for 1:1 mode operation. this mode is intended for factory use only. note: the ac timing specifications given in the document do not apply in pll-bypass mode. 4. in clock - off mode, no clocking occurs inside the powerpc 750cx regardless of the sysclk input. 5. the sysclk limit is 133mhz, as specified in table 6 on page 15. applications requiring sysclk over 133mhz will be investigated by application conditions. 6. vco max is specified in this table by the maximum core processor speed. the vco maximum of 1ghz reflects a processor core speed of 500mhz.
powerpc 750cx risc microprocessor datasheet jun 20, 2001 version 1.2 page 31 7.2 pll power supply filtering the av dd power signal is provided on the powerpc 750cx to provide power to the clock generation phase-locked loop. to ensure stability of the internal clock, the power supplied to the av dd input signal should be ?ltered using a circuit similar to the one shown in figure 15. the circuit should be placed as close as possible to the av dd pin to ensure it ?lters out as much noise as possible. the referenced ferrite bead, fb, shown in figure 14 should supply an impedance of approximately 30 ohms in the 100 mhz region. 7.3 decoupling recommendations due to the powerpc 750cxs feature large address and data buses, and high operating frequencies, the powerpc 750cx can generate transient power surges and high frequency noise in its power supply, especially while driving large capaci- tive loads. this noise must be prevented from reaching other components in the powerpc 750cx system, and the pow- erpc 750cx itself requires a clean, tightly regulated source of power. therefore, it is strongly recommended that the system designer place at least one decoupling capacitor with a low esr (effective series resistance) rating at each v dd and ov dd pin of the powerpc 750cx. it is also recommended that these decoupling capacitors receive their power from separate v dd , ov dd , and gnd power planes in the pcb, utilizing short traces to minimize inductance. these capacitors should range in value from 220pf to 10uf to provide both high and low-frequency ?ltering, and should be placed as close as possible to their associated v dd or ov dd pins. suggested values for the v dd pins: 220pf (ceramic x7r), 0.01uf(ceramic x7r), and 0.1uf(ceramic x7r). suggested values for the ov dd pins: 0.01uf(ceramic x7r), 0.1uf(ceramic x7r), and 10 m f (tantalum). only smt (surface-mount technology) capacitors should be used to mini- mize lead inductance. in addition, it is recommended that there be several bulk storage capacitors distributed around the pcb, feeding the v dd and ov dd planes, to enable quick recharging of the smaller chip capacitors. these bulk capacitors should have a low esr (equivalent series resistance) rating to ensure the quick response time necessary. they should also be connected to the power and ground planes through two vias to minimize inductance. suggested bulk capacitors: 100uf(avx tps tantalum) or 330uf(avx tps tantalum). 7.4 connection recommendations to ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. unused active low inputs should be tied to ov dd . unused active high inputs should be connected to gnd. all nc (no-connect) signals must remain unconnected. power and ground connections must be made to all external v dd , ov dd , and gnd pins of the powerpc 750cx. figure 15. pll power supply filter circuit v dd av dd 2 w 10 m f 0.1 m f gnd fb
powerpc 750cx risc microprocessor datasheet page 32 version 1.2 jun 20, 2001 7.5 output buffer dc impedance the powerpc 750cx 60x drivers were characterized over various process, voltage, and temperature conditions. to measure z 0 , an external resistor is connected to the chip pad, either to ov dd or gnd. then the value of the resistor is varied until the pad voltage is ov dd /2; see figure 16 below. the output impedance is actually the average of two resistances: the resistance of the pull-up and the resistance of pull- down devices. when data is held low, sw1 is closed (sw2 is open), and r n is trimmed until pad = ov dd /2. r n then becomes the resistance of the pull-down devices. when data is held high, sw2 is closed (sw1 is open), and r p is trimmed until pad = ov dd /2. r p then becomes the resistance of the pull-up devices. with a properly designed driver r p and r n are close to each other in value, then z 0 = (r p + r n )/2. the following table summarizes the impedance a board designer would design to for a typical process. figure 16. driver impedance measurement table 15: driver impedance characteristics process 60ximpedance ( w) v dd , ov dd (v) temperature (c) worst 65 1.70 105 typical 50 1.8 65 best 40 1.90 0 worst 65 2.38 105 typical 50 2.5 65 best 40 2.62 0 data ov dd r n sw2 sw1 pad r p gnd
powerpc 750cx risc microprocessor datasheet jun 20, 2001 version 1.2 page 33 7.5.1 input-output usage table 16 provides details on the input-ouput usage of the powerpc 750cx risc microprocessor signals. the column titled usage group refers to the general functional category of the signal. in the powerpc 750cx risc microprocessor, certain input-output signals have pullups and pulldowns, which may or may not be enabled. the column titled i/o with internal resistors de?nes which signals have these pullups or pull- downs, and their active or inactive state. the column titled level protect de?nes which signals have the designated function added to their i/o cell. refer to section 7.9.1 level protection, on page 38 for more information.
jun 20, 2001 version 1.2 powerpc 750cx risc microprocessor datasheet page 34 table 16: input-output usage powerpc 750cx signal name active level input/ output usage group i/o with internal resistors level protect required external resistor comments a0-31 n/a bidi address bus keeper see note 1 aa ck low in address termination keeper has to be actively driven ar tr y low bidi address termination keeper resistor by design needs pullup dd2.0 also bg low in address arbitration keeper active driver or pulldown br low out address arbitration keeper chip actively drives bvsel n/a in i/o level keeper 5k dd1.0, 2.0, 2.1, 2.2 sel high or low as design ci low out transfer attributes keeper see note 1 ckstp_in low in interrupt/resets keeper has to be actively driven ckstp_out low out interrupt/resets keeper no requirement dbg low in data arbitration keeper active driver or tie low dh0-31 n/a bidi data bus keeper see note 1 dl0-31 n/a bidi data bus keeper see note 1 gbl low bidi transfer attributes keeper see note 1 hreset low in interrupt/resets keeper active driver and see note 2. int low in interrupt/resets keeper active driver or pullup l1_tstclk n/a in lssd not enabled 5k dd1.0, 2.0, 2.1, 2.2 pullup required l2_tstclk/ dbw o low in lssd not enabled 5k dd1.0, 2.0, 2.1, 2.2 pullup required lssd_mode low in lssd not enabled 5k dd1.0, 2.0, 2.1, 2.2 pullup required mcp low in interrupt/resets keeper active driver or pullup pll_cfg (0-3) n/a in clock control keeper as required pullup/pulldown, as required qa ck low in status/control keeper has to be actively driven qreq low out status/control keeper chip actively drives sreset low in interrupt/resets keeper active driver or pullup, see note 2. note: 1. depends on the system design 2. hreset, sreset, and trst are signals used for esp and riscwatch to enable proper operation of the debuggers. logical and gates should be placed bet ween these signals and powerpc 750cx risc microprocessor. (refer to figure 17 on page 36.)
page 35 version 1.2 powerpc 750cx risc microprocessor datasheet jun 20, 2001 sysclk low in clock control keeper no resistor by design active driver t a low in data termination keeper active driver tbst low bidi transfer attributes keeper see note 1 tck high in jtag not enabled ext. pulldown tdi high in jtag enabled high internal- enabled 50 m a@2.5v, 25 m a@1.8v is the pullup current for the internal resistor. tdo high out jtag keeper tea low in data termination keeper active driver or pullup tms high in jtag enabled high internal- enabled 50 m a@2.5v, 25 m a@1.8v is the pullup current for the internal resistor. trst low in jtag enabled high internal- enabled see note 2 50 m a@2.5v, 25 m a@1.8v is the pullup current for the internal resistor. ts low bidi address start keeper 5k dd1.0, 2.0, 2.1, 2.2 pullup required tsiz0_tsiz2 n/a out transfer attributes keeper see note 1 tt0-4 n/a in transfer attributes keeper see note 1 wt low out transfer attributes keeper see note 1 table 16: input-output usage (cont.) powerpc 750cx signal name active level input/ output usage group i/o with internal resistors level protect required external resistor comments note: 1. depends on the system design 2. hreset, sreset, and trst are signals used for esp and riscwatch to enable proper operation of the debuggers. logical and gates should be placed bet ween these signals and powerpc 750cx risc microprocessor. (refer to figure 17 on page 36.)
powerpc 750cx risc microprocessor datasheet page 36 version 1.2 jun 20, 2001 7.6 thermal management information this section provides thermal management information for the pbga package for air cooled applications. proper ther- mal control design is primarily dependent upon the system-level design and air ?ow. 7.7 heat sink considerations the powerpc 750cx risc microprocessor package will support a maximum normal load of 2.2 kilograms. this load includes the heat sink and any forces used to position or fasten the heat sink. 7.8 internal package conduction resistance for the pbga, described in table 3 on page 12, the primary intrinsic conduction thermal resistance paths are as follows. ? die junction-to-case thermal resistance ? die junction-to-lead thermal resistance ? die junction-to-ambient thermal resistance figure 18 depicts the primary heat transfer path for this package. figure 17. ibm riscwatch tm jtag to hreset, trst, and sreset signal connector hreset from riscwatch system hreset hreset to powerpc 750cx trst to powerpc 750cx sreset to powerpc 750cx sreset from riscwatch system sreset trst from riscwatch note: see notes for table 16, input-output usage on page 34.
powerpc 750cx risc microprocessor datasheet jun 20, 2001 version 1.2 page 37 figure 18. pbga package with thermal model external resistance external resistance internal resistance (note the internal versus external package resistance.) radiation convection radiation convection die/case ( q jc ) printed-circuit board package/leads ( q jb ) chip junction q ja
powerpc 750cx risc microprocessor datasheet page 38 version 1.2 jun 20, 2001 7.9 operational and design considerations 7.9.1 level protection a level protection feature is included in the powerpc 750cx risc microprocessor in releases dd2.0 and later. the level protection feature is available only in the 1.8v bus mode. this feature prevents ambiguous ?oating reference volt- ages by pulling the respective signal line to the last valid or nearest valid state. for example, if the i/o voltage level is closer to ov dd , the circuit pulls the i/o level to ov dd ; if the i/o level is closer to gnd, the i/o level is pulled low. this self-latching circuitry keeps the ?oating inputs de?ned and avoids meta-stabil- ity. in table 16, these signals are de?ned as keeper in the "level protect" column. the level protect circuitry provides no additional leakage current to the signal i/o; however, some amount of current must be applied to the keeper node to overcome the level protection latch. this current is process dependent, but in no case is the current required over 100 m a. this feature allows the system designer to limit the number of resistors in the design and optimize placement and reduce costs. 7.9.2 64 or 32-bit data bus mode typical operation is considered to be in 64-bit data bus mode. mode setting is determined by the state of the mode sig- nal ( qa ck) at the transition of hreset from its active to inactive state (low to high). if qa ck is low when hreset transitions from active to inactive, 64-bit mode is selected. if qa ck is high when hreset transitions from active to inactive, 32-bit mode is selected. 7.9.3 1.8v and 2.5v i/o signal support selection between 1.8v and 2.5v i/o is accomplished using the bvsel pin. if bvsel is set low then the 1.8v mode is enabled. if bvsel is set high, then the 2.5v mode is enabled. due to bus timings restrictions, only uniprocessor imple- mentations are recommended. no multiprocessor support is advised.
powerpc 750cx risc microprocessor datasheet jun 20, 2001 version 1.2 page 39 7.9.4 dbw o/l2_tstclk one pin has two functions: dbw o and l2_tstclk dependent upon the lssd_mode pin. when the lssd_mode pin is low, the dbw o/l2_tstclk pin is set to l2_tstclk function which is used during the manufacturing process for testing. when the lssd_mode pin is pulled to the high state, the dbw o/l2_tstclk pin is set to dbw o which is identical to those descriptions given in earlier versions of the powerpc 750cx risc microprocessors users manuals. 7.9.5 powerpc 750cx revision level migration the following table summarizes the design changes for the respective powerpc 750cx design revision lev- els. 8.0 ordering information this section provides the part numbering nomenclature for the powerpc 750cx. note that the individual part numbers correspond to a maximum processor core frequency. for available frequencies, contact your local ibm sales of?ce. in addition to the processor frequency and bus ratio, the part numbering scheme also consists of a part modi?er. the part modi?er allows for the availability of future enhanced parts (i.e., lower voltage, lower power, higher performance, etc.). each part number also contains a revision code. this refers to the die mask revision number and is speci?ed in the part numbering scheme for identi?cation purposes only. figure 19 provides the ibm part numbering nomenclature for the powerpc 750cx. table 17: summary of design migration dd1.0 dd2.0 dd2.1 dd2.2 pvr 0x00080100 0x00080100 0x00082201 0x00082202 l1 data bus width 64-bits 256-bits 256-bits 256-bits dpm enabled disabled disabled disabled test pin chkstp_out removed clkout/ chkstp_out share a pin clkout/ chkstp_out share a pin clkout/ chkstp_out share a pin 32-bit mode not available available available available floating bus pull-ups required no pull-ups no pull-ups no pull-ups dbw o pin absent absent present present
powerpc 750cx risc microprocessor datasheet page 40 version 1.2 jun 20, 2001 9.0 processor version register (pvr) the powerpc 750cx risc microprocessor has the following pvr values for the respective design revision levels. figure 19. ibm part number key table 18: process version register (pvr) design revision level pvr dd1.0 00080100 dd2.0 00080100 dd2.1 00082201 dd2.2 00082202 ibm25ppc750cxCdp10C3t company id microprocessor family code powerpc family code powerpc product type marketing name extension reserved reserved shipping container reliability grade performance sort package type design revision level design revision level a = dd1.0 b = dd2.0 c = dd2.1 d = dd2.2 package p = plastic/laminate ball grid array performance sort contact ibm sales representative for specific offerings reliability grade contact ibm sales representative for specific offerings shipping container t = tray
powerpc 750cx risc microprocessor datasheet june 20, 2001 version 1.2 page 41 10.0 document history table 19: document history date version page description 3/31/00 1.0 initial release. 4/6/00 first revision. 4/10/00 added table 13. 4/25/00 added note 5, table 1. 11/13/00 1.1 9 minor edits to features section. 13 updated table 4, dc electrical speci?cations, on page 13 (output high voltage) 14 updated table 5, power consumption (full-on mode values). 17 figure 4, mode select input timing diagram, v ih changed to 1.24v. edited corresponding table 8, note #1. 21 edited table note #1 in table 8, trst timing diagram. 22 heading title changed (section 6.0 on page 22) and updated mechanical drawing dimensions. 23 updated figure 11, pinout of the 256 pbga package as viewed from solder ball side. 24 updated figure 12, side pro?le view of pbga. 24 updated figure 13, side pro?le view showing exposed cavity. 25 corrections to figure 14, powerpc 750cx microprocessor ball placement. 34 updated table 16, input-output usage to include dd2.2. 35 changed qreg to qreq. 38 edited section 7.9.1, level protection, on page 38 (redundant with section 7.5.1, input-output usage, on page 33). 39 edited section 7.9.4, dbwo/l2_tstclk. 39 added section 7.9.5, powerpc 750cx revision level migration. 40 updated figure 19, ibm part number key. 6/20/01 1.2 1 version update. 8 250k l2 cache line around removed. 12 note added 1. 14 table updated. 433mhz column removed. 27 removed note from table 11. 29 called out avdd in table 13. 30 table 14 updated for 500mhz max. 38 added a bus timing note in section 7.9.3. 40 updated part number decoder. speci?cs removed, to be put in supplement. 44 blank removed.
? international business machines corporation 2000 printed in the united states of america june 20, 2001 all rights reserved the information contained in this document is subject to change without notice. the products described in this document are not intended for use in implantation or other life support applications where malfunction may result in injury or death to per- sons. the information contained in this document does not affect or change ibms product specifications or warranties. noth- ing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of ibm or third parties. all information contained in this document was obtained in specific environments, and is presented as illustration. the results obtained in other operating environments may vary. while the information contained herein is believed to be accurate, such information is preliminary, and should not be relied upon for accuracy or completeness, and no representations or warranties of accuracy or completeness are made. the information contained in this document is provided on an as is basis. in no event will ibm be liable for any damages arising directly or indirectly from any use of the information contained in this document. ibm microelectronics division 1580 route 52, bldg. 504 hopewell junction, ny 12533-6531 the ibm home page can be found at http://www.ibm.com the ibm microelectronics division home page can be found at http://www.chips.ibm.com

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